1. Field of the Invention
This invention relates to semiconductor device testing, and more specifically to determining an IDDQ qualification limit for an integrated circuit.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Complementary metal oxide silicon (CMOS) integrated circuits are used in a variety of applications due to their low power consumption characteristics. In particular, CMOS circuits typically require low voltage and/or current levels and thus, are included in a variety of devices. In general, an ideal CMOS circuit conducts a negligible amount of current when in a standby or a quiescent state. Such a standby state current is primarily caused by substrate leakage and may be referred to as the source to drain quiescent current (IDDQ), the quiescent current, or the substrate leakage current. When the CMOS is in an active state, the current in the device may be referred to as the source to drain dynamic current (IDD) or saturation current. In some embodiments, however, the presence of a defect within a circuit may undesirably affect current flow through the circuit. In particular, a defect may increase or limit the flow of current through the circuit while in a standby or active state. Such an alteration of current flow may undesirably affect the functionality of the circuit, rendering the device defective.
Therefore, in the manufacture of semiconductor devices, it is important to test for defects such that the shipment of defective devices may be prevented. Such testing may occur during the fabrication of the devices and/or after the fabrication of the devices. One well-known method of testing circuits in the semiconductor fabrication industry is xe2x80x9cstatic IDD testingxe2x80x9d or xe2x80x9cIDDQ testing.xe2x80x9d The test is conventionally used to screen for reliability defects, such as open and short circuits, in CMOS memory and logic devices. In general, the test measures the amount of substrate leakage current or IDDQ current through a circuit. The amount of IDDQ current in a circuit is typically a good indication of chip quality. In particular, the lower the magnitude of the IDDQ current, the better the chip quality. As stated above, defects may cause an increase in IDDQ current within a circuit. As such, a circuit with one or more defects may draw a significantly larger amount of quiescent current than a circuit comprising fewer or no defects. Consequently, IDDQ testing may be used to determine the presence of defects within a circuit. In addition, IDDQ testing may be used to segregate defective devices from non-defective devices.
Typically, IDDQ testing involves setting a threshold value of current by which to either pass or reject the circuit (i.e., deem the circuit non-defective or defective). For example, if the IDDQ current conducted by the circuit exceeds the threshold value, the circuit will be deemed xe2x80x9cdefectivexe2x80x9d such that it is not sold to a customer. Alternatively, if the IDDQ current conducted by the circuit is less than the threshold value, the circuit will be deemed non-defective and be passed on for further processing. Currently, the threshold value is determined by analysis of empirical data and is set periodically for a given process. Such a process, however, does not account for lot-to-lot, wafer-to-wafer, or across wafer variation within a fabrication process. As such, the set threshold value may not be representative of the substrate leakage current of a circuit within a specific lot of wafers, a single wafer, or within a region of a wafer. In addition, there is generally a trade-off between passing quality circuits and producing acceptable production yields when setting such a threshold value. In particular, if the threshold value is set too high, circuits with defects may be passed through, thereby degrading the overall quality of the circuit population. In contrast, if the threshold value is set too low, circuit without defects may be rejected by the IDDQ test, thereby unnecessarily reducing production yield.
Another disadvantage of current IDDQ testing methods is that they can only detect defects that cause an IDDQ current larger than the background leakage current (i.e., the substrate leakage current of the device when no defects are present in the circuit). As such, current IDDQ testing methods require low background leakage current while in the quiescent state. As dimensions of semiconductor devices become smaller, however, the background leakage current of devices increases. For example, smaller channel lengths generally result in greater background leakage current. In addition, the reduction of semiconductor device sizes has enabled more transistors to be fabricated on a die, thereby increasing the overall background leakage current. Furthermore, smaller transistors typically produce lower saturation current, thereby reducing the variation between the IDDQ current and IDD current.
Therefore, it would be advantageous to create a method for determining an IDDQ threshold value for an integrated circuit that overcomes the limitations of conventional techniques used for determining such values. Such a method may be particularly advantageous for determining a threshold value of an integrated circuit within a specific lot, wafer, or a region of a wafer.
The problems outlined above are in large part addressed by a method for determining an IDDQ test limit of an integrated circuit. In particular, a method is provided which includes measuring the IDDQ value of a test structure formed upon a die and setting the IDDQ test limit of an integrated circuit based upon the measured IDDQ value of the test structure. In a preferred embodiment, the die may be derived from the same lot of wafers as the integrated circuit. In some embodiments, the die may be derived from the same wafer as the integrated circuit. In particular, the die upon which the test structure is formed may be derived from the same region of the wafer as the die upon which the integrated circuit is formed. In some cases, the die upon which the test structure is formed may include the integrated circuit. In addition or alternatively, the method may further include forming one or more test structures on each die of the lot of wafers. In some cases, the method may include measuring IDDQ values of a plurality of the one or more test structures and setting the IDDQ test limit of the test integrated circuit based upon the measured IDDQ values. In either embodiment, the method may be conducted when the die is included within a semiconductor wafer or when the die is separated from a wafer. As such, the method may further include dicing each wafer of the lot of wafers, in which the test structure and integrated circuit are formed. In some embodiments, measuring the IDDQ value of the test structure may be conducted prior to dicing each wafer. In other embodiments, measuring the IDDQ value of the test structure may be conducted subsequent to dicing each wafer.
In some cases, setting the IDDQ test limit may include correlating the IDDQ value of the test structure to calibration data to determine the IDDQ test limit. As such, a means for determining an IDDQ test limit of an integrated circuit is also contemplated herein. Such a means may include a test structure and calibration data that is adapted to correlate an IDDQ value measured from the test structure to an IDDQ test limit of the integrated circuit. In some embodiments, the test structure may be formed upon a die, which is derived from the same lot of wafers as a die upon which the integrated circuit is formed. In some cases, the test structure may be formed upon the same die as the integrated circuit. In yet other cases, the means for determining an IDDQ test limit of an integrated circuit may include one or more additional test structures formed upon other die that are derived from the same lot of wafers as the die upon which the integrated circuit is formed. In such an embodiment, the calibration data may be further adapted to correlate IDDQ values measured from the one or more additional test structures to the IDDQ test limit of the integrated circuit. In either embodiment, the test structure is preferably electrically isolated from the integrated circuit.
In some embodiments, the test structure may include an aspect ratio sufficient to generate a substrate leakage current of the test structure to a level detectable by the automatic test equipment used to measure the IDDQ current of the test structure. In addition or alternatively, the means for determining an IDDQ test limit of an integrated circuit may include a means for increasing a substrate leakage current of the test structure to a level detectable by the automatic test equipment used to measure the IDDQ current of the test structure. In some embodiments, the means for increasing the substrate leakage current of the test structure may be adapted to increase the substrate leakage current of the test structure to a level of the same order of magnitude as an intrinsic substrate leakage current of the integrated circuit. In one case, the means for increasing the substrate leakage current of the test structure may include a substrate back bias. Such a back bias may be applied internally though the use of a back bias generator or may be applied by an external source. In other embodiments, the means for increasing the substrate leakage current of the test structure may include a system adapted to increase the temperature of the test structure, such as an internal resistance network or an external heat source.
In some embodiments, the method may further include applying a back bias to the test structure prior to measuring the IDDQ value of the test structure. In addition or alternatively, the method may include raising a temperature of the test structure prior to measuring the IDDQ value of the test structure. In some embodiments, the application of a back bias and/or the increase in temperature may be adapted to increase a substrate leakage current of the test structure to a level detectable by the automatic test equipment used to measure the IDDQ current of the test structure. In some cases, the application of the back bias and/or the increase in temperature may be adapted to increase a substrate leakage current of the test structure to a level of the same order of magnitude as an intrinsic substrate leakage current of the integrated circuit.
The method as described herein may offer several benefits. For example, the method may allow a threshold value to be set based upon the IDDQ value of a test structure formed using the same fabrication process conditions as that used to form an integrated circuit. In this manner, a threshold value may be set specifically for the integrated circuit being measured. More specifically, the threshold value may be set specifically for an integrated circuit formed within the same lot, wafer, or region of a wafer as the test structure. In this manner, variations of background leakage currents within lots of wafer, single wafers, or regions of wafers may be accounted for. Consequently, such a method may reduce or eliminate the trade-off of passing quality circuits and producing acceptable production yields during IDDQ testing. In addition, the method allows the IDDQ test limit of an integrated circuit to be determined when the die upon which the integrated circuit is formed is arranged within a semiconductor wafer or when such a die is separated from a wafer. In this manner, the IDDQ test limit of an integrated circuit may be determined during the fabrication of the device or after packaging of the device.